1. Field of the Invention
The present invention relates to a logic simulation system, in other words, a logic simulation method which previously simulates the circuit operation by a computer when a circuit using logic gates is designed, and to a computer, i.e., a simulator which is used for practical use of the logic simulation method.
2. Description of the Prior Art
Since a circuit comprising many logic circuit components, such as logic gates, is often designed at a very complex level, it is troublesome to check the circuit operation by an actual circuit. Hence, prior to construction of the actual circuit, the operation is often presimulated and checked by the computer. A logic simulator is a tool to confirm whether or not an input and an output of signal is proper after carrying out the simulation.
The conventional logic simulator determines the output of each logic circuit component by inspecting the input for a predetermined period to compute the output, so that the result of computation, as it is or only in a case of changing the output content, has been given to the sequential components.
Such logic simulation, however, is larger in a processing load and requires longer latency, whereby the simulation at a high speed has been limited.